The quest to develop larger and larger semiconductors of the dynamic random access memory (DRAM) type is a well-known goal. The industry has steadily progressed from DRAMs of the 16K type, shown in U.S. Pat. No. 4,081,701 issued to White, McAdams and Redwine, and the 64K type, shown in U.S. Pat. No. 4,055,444 issued to Rao, to DRAMs of the 1M type, as described in U.S. Pat. No. 4,658,377 issued to McElroy. DRAMs of the 4M type are now being produced. Production plans for 16M DRAMs of submicron technology now exist and experimentation of 64M DRAMs has begun. One factor furthering the development of larger DRAMs is the reduction in memory cell geometries as illustrated in U.S. Pat. No. 4,240,092 to Kuo (a planar capacitor cell), and as illustrated in U.S. Pat. No. 4,721,987 to Baglee et al, (a trench capacitor cell).
Complementary metal oxide, CMOS, semiconductor technology has been incorporated into the design of DRAM circuitry. Among other advantages, CMOS technology aids in reducing the power consumed by the DRAM device. U.S. Pat. No. 5,017,506 issued to Shen, Yashiro, McKee, and Chung, on May 21, 1991 describes a process suitable for manufacturing high density CMOS type 16M DRAMS.
In CMOS technology, it is common to create two separate tanks. A P tank and an N tank may be created on a semiconductor substrate by doping two regions of the substrate with different dopants. A field oxide may be grown on the semiconductor substrate at the intersection of the two dopants to separate the tanks from each other. Each tank contains circuits and the circuits within each tank may be further isolated from each other. For example, circuits within the N tank may be isolated from each other by forming a P tank between the N tanks and covering the P tank with a field oxide.
In manufacturing high density CMOS products such as DRAMs, it becomes difficult to isolate circuits within one of the tanks from each other. In the example of separating circuits within the N tank by a P tank, the standard CMOS process first forms the P tank and then forms the field oxide it. When this field oxide is grown, the segregation coefficient tends to drag the P tank dopant (boron e.g.) into the oxide and reject the N tank dopant (phosphor e.g.). The phosphor dopant may then laterally diffuse across the top of the P tank near the surface of the semiconductor chip. This can result in electrical shorting between the N tanks.
It is an object of this invention to provide a blocking mechanism for CMOS devices to prevent tank shorting. It is a further object of this invention to provide a channel stop structure for high density DRAM memory devices.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification and drawings.